1. Field of the Invention
The present invention relates to a method for inspecting a photoresist pattern. In particular, the present invention relates to a method for inspecting a photoresist pattern by measuring the current of a PN junction.
2. Description of the Prior Art
In regular standard semiconductor processes, an ion implantation procedure is often used to adjust the conductivity types of the materials, to define certain specific regions and to construct the needed elements. The procedures to operate the ion implantation usually first involve using a mask, a patterned photoresist for example, to expose the region which needs the ion implantation and to mask the region which does not need the ion implantation. Later, suiChart dopants are used and proper energy range is determined to construct the doped regions with expected concentrations and depth followed by suiChart thermal activation.
Generally speaking, the exposure and development techniques are frequently used in patterning the photoresist to transfer the pre-determined pattern on the reticles onto the photoresist. With the progressive trend of shrinkage of the critical dimension (CD), the off-set issue between the photoresist pattern to be formed and the existing pattern on the substrate is getting more and more serious since the dopants may not be formed on the expected regions correctly or completely. Moreover, the patterned photoresist may cause the regions to be implanted overly large, overly small, closed or distorted due to various reasons, such as exposure failure or incomplete development, during the exposure and development procedures. No matter what the cause is, any one of them would eventually compromise the usage and operation of the final semiconductor.
There are two known methods which are currently employed to inspect the minimum regions and the enclosure regions of the doped layer photoresist in the standard logic process. The first one is called “DOF simulation tool.” In this method, the DOF simulation tool is used to predict the minimum regions and the enclosure regions of the doped layer photoresist in the standard logic process. Because the DOF simulation tool does not predict the minimum regions and the enclosure regions of the doped layer photoresist in the standard logic process in accordance with the data obtained following the ion implantation procedure, judged by the empirical viewpoint, the predicted results by the DOF simulation tool are more often than not too ideal to practically reflect the actual status of the regions on the doped layer photoresist.
The other method is called “In Line Data Check.” The bottom scum or top rounding of the photoresist is “hand-picked” by naked eyes along with proper apparatuses. Apparently, any inspection judged by naked eyes is too difficult and too subjective. Second, this method only “physically” inspects the physical shape of the photoresist, which fails to practically reflect the actual status of the regions on the doped layer photoresist, either.
Accordingly, a novel method for inspecting a photoresist pattern is still needed to obtain the first-hand information regarding the actual status of the minimum regions and the enclosure regions of the doped layer photoresist in the standard logic process. This novel method should not be too ideal to practically reflect the actual status of the minimum regions and the enclosure regions of the doped layer photoresist in the standard logic process.